1. Field of the Invention
The present invention relates to a circuit arrangement for telecommunications systems, and more particularly for telephone systems, wherein information incoming via a data bus and comprising a plurality of bits, particularly of a byte, together with a write instruction via a first buffer serving for intermediate storage of respectively only one information are supplied to a main memory system serving for storage of a plurality of information at the same time. The main memory systems comprises, in particular, a dynamic memory portion, an information taken from the main memory system by way of a read instruction and offered by the main memory system chronologically limited are emitted onto the data bus via a second buffer until the end of the read instruction. Given storage of the incoming information by way of a parity evaluator, respectively one parity bit per information is formed and stored together with the respective information and, given output of a respective information from the main memory system, one parity bit per information is again derived from the information and is compared to the stored parity bit.
2. Description of the Prior Art
It has been provided in prior instances of circuit arrangements of the general type set forth above, that a parity evaluator between the first buffer and the main memory system is also connected to an internal memory data bus connecting the buffer and the main memory system. When the information transmitted to the main memory system via the buffer and via the data bus are accompanied by a respective parity bit, then the accuracy of not only the information transmission via the data bus, but also the intermediate storage in the first buffer can be co-monitored.
It turns out, however, that the monitoring of the accuracy of the storage is of considerably greater significance than a monitoring of the accuracy of the transmission of the information via the data bus.
A problem in circuit arrangements of the type set forth above is the total expenditure for the large number of memory processes to be executed. The time expense required for the subsequent parity evaluation is thereby added per storage process to the time of intermediate storage in the first buffer. Since the result of the parity evaluation must also be stored, namely assigned to the respective information, the time expense for the parity evaluation is interposed between the time of the intermediate storage in the first buffer and the acceptance of the appertaining information in the main memory system.